“Virtual substrates” based on silicon (Si) and germanium (Ge) provide a platform for new generations of very large scale integration (VLSI) devices that exhibit enhanced performance in comparison to devices fabricated on bulk Si substrates. The important component of a SiGe virtual substrate is a layer of SiGe that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si). This relaxed SiGe layer may be directly applied to a Si substrate (e.g., by wafer bonding or direct epitaxy), or atop a relaxed graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer. To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or SiGe, are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters the carrier mobilities in the layers, enabling the fabrication of high-speed and/or low-power-consumption devices. The thin strained semiconductor layers may also be subsequently transferred to other substrates having insulator layers by methods such as wafer bonding, thus creating strained-semiconductor-on-insulator (SSOI) wafers.
In certain cases the microstructure of semiconductor graded buffer layers as grown may be less than ideal depending on the growth conditions. For example, SiGe buffer layers deposited at temperatures below 850° C. may not attain the relaxation state desired for strained Si applications, i.e., >98%. In addition, the density of threading dislocations may be higher than desired. Furthermore, both high and low temperature growth conditions may result in as-grown graded buffer layers having top surfaces that are rougher than the ultra-planar surfaces preferable for growth of relaxed semiconductor cap layers with subsequent strained semiconductor layer deposition (e.g., regrowth of SiGe layers containing 20% Ge, followed by deposition of strained Si). This roughness may carry over and increase in subsequently formed layers. In addition, roughness on a layer surface negatively impacts the ability of laser scanning tools to perform optical inspection for defects in the layer before and after planarization and regrowth. Roughness appears in the scattered signal of the laser scanner as an elevated level of “haze” or background noise, reducing the ability of the tool to detect small defects in and on the layer. It is desirable, therefore, to reduce this roughness in semiconductor layers.